Vertical type semiconductor device

ABSTRACT

In a vertical type MOSFET device having a super junction structure, in which a N conductive type column region and a P conductive type column region are alternately aligned, regarding to a distance between a terminal end of an active region and a terminal end of a column region, the terminal end of the column region is disposed at a position, which is separated from the active region terminal end by a distance obtained by subtracting a half of a width of the N conductive type column region from a distance corresponding to a depth of the column region. Thus, an electric field concentration at a specific portion in a region facing a narrow side of the column structure is prevented so that a breakdown voltage of the vertical type MOSFET is improved.

FIELD OF THE INVENTION

The present invention is related to a vertical type semiconductor devicehaving high breakdown voltage, which is, for example, suitable for MOS.

BACKGROUND ART

A structure of a conventional vertical type MOS field effect transistor(i.e., a vertical type MOSFET) or the like is shown in FIG. 11 (SeeJapanese Patent Application Publication No. 2002-184985). In thestructure, a N conductive type semiconductor region 2 and a P conductivetype semiconductor region 3 are disposed in a trench having apredetermined depth in a substrate depth direction. These regions 2, 3are alternately aligned on a semiconductor substrate 1. This is acolumnar structure known as “a super-junction structure.” A columnregion 4 having the columnar structure is formed on the semiconductorsubstrate 1. An active region 13 is formed on the column region 4 sothat a device structure having high breakdown voltage and low on-stateresistance is provided. The active region 13 is composed of a sourceregion 7, a gate region 11 and a body region 6.

In an outer periphery 141 of the column region, it is important toincrease a breakdown voltage at a connection between a N conductive typesemiconductor region (i.e., a N conductive type column region 2) and a Pconductive type semiconductor region (i.e., a P conductive type columnregion 3). Accordingly, the conventional vertical type MOSFET has across section, in which the N conductive type column region 2 and the Pconductive type column region 3 are aligned on the semiconductorsubstrate 1 alternately. A distance from an utmost outer periphery ofthe active region 13 to a terminal end 16 of the column region 4 isequal to or larger than a depth of the column region 4.

FIG. 2A is a layout chart showing the column region 4, which isconstructed such that the N conductive type column region 2 and the Pconductive type column region 3 are alternately aligned on thesemiconductor substrate.

A shown in FIG. 2A, the P conductive type column region 3 is constructedsuch that multiple regions are aligned as a rectangular striped shape,and each region has a polygonal shape. Here, the polygon having therectangular striped shape has a pair of wide sides, which face eachother. Further, the polygon has another pair of narrow sides, which aredisposed on both ends of the wide sides. Accordingly, for example, incase of a quadrangle, the polygon is obtained by spreading one pair offacing sides of the quadrangle having two pair of facing sides. Thespread sides provide wide sides, and the other sides provide narrowsides. In a case where the polygon is a hexagon, one pair of facingsides is spread so that the one pair of spread sides provides a pair ofwide sides, and the other two pairs of facing sides provide two pairs ofnarrow sides. Here, in FIG. 2A, the active region 13 is shown as adashed line so that the positioning relationship of the active region 13is clearly defined.

Conventionally, a structure having a cross section along with line IA—IAin FIG. 2A is well-known. The IA—IA cross section corresponds to aregion facing the wide side of the P conductive type column region inthe structure, in which the N conductive type column region 2 and the Pconductive type column region 3 are alternately aligned with arectangular striped shape on the semiconductor substrate.

However, it has not studied substantially about an effective structureof a structure corresponding to the IB—IB cross section shown in FIG.2B. The IB—IB cross section corresponds to the region facing the narrowside of the P conductive type column region 3. On the substrate surface,it is obvious that the breakdown voltage becomes larger as the distancefrom the utmost outer periphery of the active region 13 to the terminalend of the column region 4 becomes longer. In general, it is requiredfor the semiconductor device to become minimized. Therefore, it isrequired to produce a condition for meeting with a small sized devicehaving high breakdown voltage and low on-state resistance.

In view of the above problem, it is an object of the present inventionto provide a structure providing a small sized device having sufficientbreakdown voltage and sufficient on-state resistance in a high breakdownvoltage semiconductor device, in which a N conductive type column regionand a P conductive type column region are alternately aligned on asemiconductor substrate.

DISCLOSURE OF THE INVENTION

To obtain the above object, the inventors have studied about thedistance between the terminal end 17 of the active region 13 and theterminal end 16 of the narrow side of the P conductive type columnregion 3 in the column region 4. The terminal end 17 of the activeregion 13 is determined as a terminal end of a body contact region. Thedistance is defined as a terminal end region length L. The inventorshave obtained knowledge that it is required for the terminal end regionlength L to be equal to the depth of a depletion layer spreading in asubstrate depth direction of the column region when the column region iscompletely depleted.

The outline of this knowledge is explained with reference to thedrawings. FIG. 3 is a partial cross sectional view showing the structureof the column region 4, in which the N conductive type column region 2and the P conductive type column region 3 are alternately aligned. Asshown in this drawing, the region comprising the N conductive typecolumn region 2 and the P conductive type column region 3 is designed todeplete the column region 4 completely. Specifically, the region isdesigned in such a manner that a half of a width (i.e., W_(N) or W_(P))of each column region in a horizontal direction of a substrate surfaceis depleted, respectively, and full depth (i.e., D) of each columnregion in a vertical direction of the substrate surface is depleted,respectively. To determine the breakdown voltage of the semiconductordevice on the basis of the column structure, it is required for thewidth of the depletion layer spreading in the horizontal direction ofthe substrate surface to be equal to the depth of the depletion layerspreading in the vertical direction of the substrate. Thus, the distancefrom the terminal end 17 of the active region 13 defined as a terminalend of the body contact region 8 to the terminal end 16 of the columnregion 4 is necessitated to design as follows.

The designing of the distance is explained with reference to FIG. 4,which is a perspective cross sectional view showing the semiconductordevice having the column structure. When the device is applied to thebreakdown voltage, the terminal end of the depletion layer, i.e., theutmost outer periphery of the depletion layer spreading from theterminal end of the active region 13 in the horizontal direction of thesubstrate is disposed outside of the terminal end 16 of the columnregion by a length of a half of the width (i.e., W_(N)) of the Nconductive type column region. Accordingly, the terminal end 16 of thecolumn region is disposed at a position, which is separated from theterminal end 17 of the active region by a distance obtained bysubtracting the length of a half of the width of the N conductive typecolumn region from the distance corresponding to the depth (i.e., D) ofthe column region. In this case, the depletion layer spreading in aregion facing the narrow side of the P conductive type column region 3spreads to be equivalent to the depletion layer spreading in thevertical direction of the substrate surface. Therefore, electric fielddoes not concentrate at a specific part in the depletion layer.

Thus, the distance from the terminal end 17 of the active region facingthe narrow side of the active region to a P-N junction disposed at theterminal end 16 of the column region facing the narrow side of thecolumn region is defined as a terminal end region length L. When thelength L satisfies the numerical formula No. 1, there is no portionhaving low breakdown voltage lower than a design value. Thus, it ispossible to design and manufacture the vertical type semiconductordevice having minimum dimensions, sufficient breakdown voltage andsufficient on-state resistance.L+W _(N)/2≧D  (Numerical formula No. 1)

Here, L represents the terminal end region length, W_(N) represents thewidth of the N conductive type column region, and D represents the depthof the column structure.

In the present invention, the terminal end region length L is defined asthe distance between the terminal end of the body contact region (8) asthe terminal end (17) of the active region to the terminal end (16) ofthe column region. The width of the first semicodncutor region (2) isdefined as W₁, and the depth of the column region is defined as D. Thepresent invention is characterized in that the device is designed tosatisfy the formula of L≧D−W₁/2.

Thus, it is possible that the width of the depletion layer spreadingfrom the inside of the column region (4) toward the terminal end (16) ofthe column region spreads to be equivalent to the width of the depletionlayer spreading from the inside of the column region in the depthdirection of the substrate. Thus, the electric field is prevented fromconcentrating at a specific part in a region facing the narrow side ofthe column structure. The breakdown voltage of the vertical typesemiconductor device (i.e., the vertical type MOSFET) is improved.

In another embodiment of the present invention, the vertical typesemiconductor device is formed on a (110)-Si surface substrate having afirst conductive type, and the device includes a semiconductor region(3), which has a second conductive type and has an outline (i.e., outershape) composed of a surface including at least one pair of a (111)-Sisurface of silicon crystal. The distance from the terminal end of thebody contact region (8) providing the terminal end (17) of the activeregion to the terminal end portion (16) disposed on the narrow side ofthe second semiconductor region (3) in the column region (4) is definedas the terminal end region length L. The first semiconductor regionwidth is defined as W₁, and the column structure depth is defined as D.The other embodiment is characterized in that the device is constructedto satisfy the relationship of L≧(D−W₁/2)/sin 35.27.

Further, in further another embodiment of the present invention, thevertical type semiconductor device is formed on a (110)-Si surfacesubstrate having a first conductive type, and the device includes asemiconductor region (3), which has a second conductive type and has anoutline (i.e., outer shape) composed of a surface including at least onepair of a (111)-Si surface of silicon crystal. The distance from theterminal end of the body contact region (8) providing the terminal end(17) of the active region to the terminal end portion (16) disposed onthe narrow side of the second semiconductor region (3) in the columnregion (4) is defined as the terminal end region length L. The firstsemiconductor region width is defined as W₁, the column structure depthis defined as D, and the depth of the body region is defined as D_(B).The further other embodiment is characterized in that the device isconstructed to satisfy the relationship of L≧{(D−W₁/2)/sin35.27}+(D_(B)/tan 35.27).

The above structures described in the other embodiments of the presentinvention enables to expand the depletion layer spreading toward theterminal end (16) of the column region to be equivalent to the depletionlayer spreading from the inside of the column region (4) in the depthdirection of the substrate. Since the electric field is prevented fromconcentrating at a specific part in a region facing the narrow side ofthe column structure, the breakdown voltage of the vertical typesemiconductor device (i.e., the vertical type MOSFET) is improved.

Here, the reference numeral in a bracket of each means described abovecorresponds to concrete means described in latter described embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are cross sectional views showing a vertical MOSFETaccording to a first embodiment of the present invention.

FIG. 2A is a layout chart showing the vertical MOSFET according to thefirst embodiment of present invention.

FIG. 2B is a layout chart showing a vertical MOSFET according to anotherexample of the first embodiment.

FIG. 2C is a layout chart showing a vertical MOSFET according to furtheranother example of the first embodiment.

FIG. 2D is a layout chart showing a vertical MOSFET according tofurthermore another example of the first embodiment.

FIG. 3 is a view explaining a spreading state of a depletion layer in acolumn region according to the present invention.

FIG. 4 is a view explaining a position of a terminal end of the columnregion according to the present invention.

FIG. 5 is a graph showing a terminal end region length L dependency ofthe breakdown voltage of the vertical type MOSFET according to the firstembodiment of the present invention.

FIGS. 6A and 6B are cross sectional views showing a vertical type MOSFETaccording to a second embodiment of the present invention.

FIGS. 7A and 7B are cross sectional views showing a vertical type MOSFETaccording to a third embodiment of the present invention.

FIG. 8 is a layout chart showing the vertical type MOSFET according tothe third embodiment of the present invention.

FIGS. 9A and 9B are cross sectional views showing a vertical type MOSFETaccording to a fourth embodiment of the present invention.

FIG. 10 is a cross sectional view showing a vertical type MOSFETaccording to a fifth embodiment of the present invention.

FIG. 11 is a view showing a conventional structure.

PREFERRED EMBODIMENTS OF THE INVENTION

(First Embodiment)

FIGS. 1A and 1B are cross sectional views showing a vertical type MOSFETaccording to a first embodiment of the present invention. FIG. 1A showsa structure corresponding to a IA—IA cross sectional view facing anarrow side of a P conductive type column region 3 shown in FIG. 2. Tounderstand this embodiment easily, FIG. 1B shows a structurecorresponding to a IB—IB cross sectional view facing a wide side of theP conductive type column region 3 shown in FIG. 2. This structure isknown conventionally.

The vertical type MOSFET shown in the above drawings is explained. Thevertical type MOSFET is formed on a semiconductor substrate having a N⁺conductive type. The MOSFET includes a N⁺ conductive type drain region1, a column region 4, a N⁺ conductive type source region 7, a Pconductive type body region 6, a P⁺ conductive type body contact region8 and a trench gate 11.

The N⁺ conductive type drain region 1 is formed from the N⁺ conductivetype semiconductor substrate. An electrode made of, for example,aluminum is mounted on a backside of the semiconductor substrate.

The column region 4 is disposed on the N⁺ conductive type drain region1. As shown in FIG. 1B, the column structure composing the column region4 is composed of the P conductive type column region 3 and the Nconductive type column region 2, which are alternately aligned. The Pconductive type column region 3 is made of P conductive typesemiconductor single crystal. The N conductive type column region 2 ismade of N conductive type semiconductor single crystal. In FIG. 1A, onlya cross section of the P conductive type column region 3 in the columnregion 4 is shown. However, actually, the N conductive type columnregion 2 exists in the column region 4. The N conductive type columnregion 2 is made of N conductive type silicon single crystal, and isdisposed adjacent to the column region 3 in the depth direction of thedrawing. The N conductive type column region 2 can be assumed as a driftregion of the vertical type MOSFET so that drain current flows throughthe N conductive type column region 2.

A N conductive type semiconductor region 21 is disposed outside of thecolumn region 4. A boundary between the N conductive type semiconductorregion 21 and the P conductive type column region 3 in FIG. 1A providesa column region terminal end 16. A P⁻ conductive type semiconductorsingle crystal region 5 is disposed on the column region 4 or on both ofthe column region 4 and the N conductive type semiconductor singlecrystal region 21 disposed outside of the column region 4.

A P conductive type body region 6 is formed on a substrate surfaceportion of the P⁻ conductive type semiconductor single crystal region 5,as shown in FIG. 1B. A N⁺ conductive type source region 7, a P⁺conductive type body contact region 8 and a trench are formed in the Pconductive type body region 6. A gate insulation film 9 is formed on asidewall and a bottom of the trench. The gate insulation film 9 is madeof, for example, silicon oxide film. An electrode made of poly siliconor the like is embedded in the trench so that a trench gate 11 isformed. The N⁺ conductive type source region 7 is disposed on thesurface of the P conductive type body region 6 and around the trenchgate 11. In this structure, when a voltage is applied to the trench gate11, a channel is formed in a region disposed along with the sidewall ofthe trench gate 11, which is sandwiched between the source region 7 andthe buffer region 12.

The P⁺ conductive type body contact region 8 is disposed on the surfaceof the P conductive type body region 6. It is enough that the P⁺conductive type body contact region 8 is formed at least in the Pconductive type body region 6, which is disposed between the trenchgates 11. The P⁺ conductive type body contact region 8 is also formed onthe surface of the P conductive type region 6, which is disposed on theutmost outer periphery of the active region 13. Thus, the electricpotential of the P conductive type body region 6, which is disposed onthe utmost outer periphery of the active region 13, can be fixed so thatparasitic operation is not occurred.

The N conductive type buffer region 12 is disposed to contact the Nconductive type column region 2 as the drift region, the trench gate 11and the P conductive type body region 6. The trench gate 11 is formed toreach the N conductive type buffer region 12. This buffer region 12 canbe formed not only under the trench gate 11 but also under the wholeactive region 13. However, it is preferred that the buffer region 12 isformed only under the trench gate 11. This is because the P conductivetype body region 6 disposed between the trench gates 11 is separatedfrom the P conductive type column region 3 electrically so that the Pconductive type body region 3 becomes a floating state.

In the vertical MOSFET having the above structure, the terminal endregion length L is defined as the distance from the active regionterminal end 17 to the P/N junction. The active region terminal end 17is determined by the utmost outer periphery of the P⁺ conductive typebody contact region 8. The P/N junction is disposed on the column regionterminal end 16. The active region 13 and the N conductive type siliconsingle crystal region 21 are formed to separate therebetween by theterminal end region length so that the terminal end region length Lsatisfies the numerical formula No. 2. Here, the numerical formula No. 2is obtained in such a manner that W_(N)/2 in the right side member ofthe numerical formula No. 1 is shifted to the left side member.L≧D+W _(N)/2  (Numerical formula No. 2)

Here, L represents the terminal end region length, W_(N) represents theN conductive type column region width, and D represents the columnstructure depth.

Further, the N conductive type single crystal region 22 is formed fromthe surface to contact the single crystal region 21. Specifically, the Nconductive type single crystal region 22 is disposed over the Nconductive type silicon single crystal region 21 and disposed outside ofthe P⁻ conductive type semiconductor single crystal region 5. Thissingle crystal region 22 is disposed from the same position of theterminal end position of the P conductive type column region 3 or fromthe outside of the terminal end position toward the outer periphery ofthe active region 13. Thus, the single crystal regions 21, 22 surroundthe utmost outer periphery of the device.

The above structure provides that the depletion layer spreading from theinside of the column region 4 toward the column region terminal end 16spreads to be equivalent to the depletion layer spreading from theinside of the column region 4 to the substrate depth direction.Accordingly, the electric field concentration at the region facing thenarrow side of the column structure is prevented so that the breakdownvoltage of the vertical type MOSFET is improved.

FIG. 5 is a graph showing terminal end region length L dependency of thebreakdown voltage in the vertical MOSFET having the design breakdownvoltage of about 220V, according to this embodiment. The vertical axisof the graph represents the breakdown voltage, the horizontal axisrepresents the terminal end region length L. When the terminal endregion length L is in a range of L<D−W_(N)/2, the breakdown voltage doesnot satisfy the design value. When the terminal end region length L isin a range of L≧D−W_(N)/2, the breakdown voltage is saturated near thedesign value. Thus, L=D−W_(N)/2 becomes the boundary. Accordingly, asshown in this graph, it is confirmed that the minimum dimension of theterminal end region length L can be described as an equation ofL≧D−W_(N)/2.

Here, as described above, the terminal end region length L is determinedby focusing only on the repeating structure of the PN junctions in thecolumn region 4. Therefore, the repeating structure of the PN junctionsbetween the buffer layer 12 and the P⁻ conductive type semiconductorsingle crystal region 5 is not considered. The PN junctions are formedin the depth of the buffer layer 12. This is because the breakdownvoltage of the vertical MOSFET according to this embodiment isdetermined by the depth of the column region 4 so that the breakdownvoltage is not determined by the buffer layer 12. Accordingly, asdescribed above, the terminal end region L is determined by onlyfocusing on the repeating structure of the PN junctions in the columnregion 4.

Further, a stripe structure shown in FIG. 2A is shown as an example ofthe column structure. The column structure can be provided by anotherstructure besides the stripe structure such as a square dot structureshown in FIG. 2B, a hexagonal dot structure shown in FIG. 2C, and acircular dot structure shown in FIG. 2D.

In these cases, the minimum dimension of the terminal end region lengthL, i.e., the distance between the active region 13 and the terminal endof the column region 4 satisfies the above described relationship. Theactive region 13 is shown as a dashed line in FIGS. 2B to 2D, and theterminal end of the column region 4 is shown as a dotted line in FIGS.2B to 2D. Here, the distance between the dots is defined as W_(N).

Further, the gate structure can be also provided by the stripe structureand a periodic structure having dot structure, similar to the columnstructure. Even when the gate structure is provided by the stripestructure, the stripe structure can have a positioning relationship notonly to be parallel to the column structure but also to be perpendicularto or tilted to the column structure.

(Second Embodiment)

FIG. 6A is a cross sectional view showing a vertical type MOSFTaccording to a second embodiment of the present invention. Thisembodiment is different from the first embodiment, the difference suchthat no P⁻ conductive type semiconductor single crystal region 5 and noN conductive type buffer region 12 in the cross sectional drawing inFIGS. 1A and 1B is disposed on the substrate surface so that the columnstructure reaches the substrate surface, which includes no P body region6.

The layout on the substrate surface corresponds to the IA—IA crosssectional structure facing the narrow side of the P conductive typecolumn region 3, that is similar to the first embodiment. Here, FIG. 6Bis described to understand this embodiment easily. FIG. 6B shows astructure corresponding to the IB—IB cross sectional structure facingthe wide side of the P conductive column region 3 shown in FIG. 2A, thestructure which is well-known conventionally.

In the second embodiment, the active region 13 and the N conductive typesemiconductor region 21 made of N conductive type silicon single crystalare formed to satisfy the numerical formula No. 2, which is the sameequation as the first embodiment.

Thus, in the second embodiment, the depletion layer spreading from theinside of the column region 4 toward the column region terminal end 16can spread to be equivalent to the depletion layer spreading toward thesubstrate depth direction of the column region 4. Accordingly, theelectric field concentration at the region facing the narrow side of thecolumn structure is prevented so that the breakdown voltage of thevertical type MOSFET is improved.

(Third Embodiment)

FIG. 7A is a cross sectional view showing a vertical type MOSFETaccording to a third embodiment of the present invention. FIG. 7A showsa structure corresponding to the VIIA—VIIA cross sectional structure,which faces the narrow side of the P conductive type column region 3shown in FIG. 8. Here, FIG. 7B is described to understand thisembodiment easily. FIG. 7B shows a structure corresponding to theVIIB—VIIB cross sectional structure facing the wide side of the Pconductive column region 3 shown in FIG. 8, the structure which iswell-known conventionally.

In the third embodiment, similar to the first embodiment, when thecolumn structure is formed, a Si substrate having a (110)-surface isused. The column structure is formed by a wet-etching method utilizing asurface orientation dependency of an etching rate. Therefore, the shapeof the column is different from that in the above described embodiments.The other fundamental structures are similar to those of the firstembodiment.

In the first and the second embodiment, the PN junction surface at thecolumn region terminal end 16 is disposed perpendicularly to thehorizontal direction of the substrate surface. However, in the thirdembodiment, as shown in FIG. 7A, the PN junction surface at the columnregion terminal end 16 has an angle of 35.27 degrees from the horizontaldirection of the substrate surface. The range of the depletion layerspreading in the substrate is almost the same as the above describedembodiment so that the depletion layer spreads in a range having alength obtained by adding the length of a half of the N conductive typecolumn region width W_(N) to the distance from the terminal end 17 ofthe active region to the terminal end 16 on the narrow side of the Pconductive type column region 3 in the column region 4. The terminal endregion length L on the substrate surface can be expressed by atrigonometric function. Specifically, the length L is expressed asfollows.

Firstly, a perpendicular line is dropped from the terminal end 17 of theactive region in the column region on the substrate surface in the depthdirection of the substrate. An intersection between the perpendicularline and the boundary between the P⁻ conductive type semiconductorregion 5 and the P conductive type column region 3 is defined as astarting point 18. A circular arc having a radius is drawn, the radiusobtained by subtracting the N conductive type column region width WNfrom the depth of the column. The circular arc contacts the (111)-Sisurface, a contact point being between the circular arc and the columnregion terminal end 16. Then, a normal line is dropped from the contactpoint to the terminal end of the column region 4. From a relationshipamong the normal line, the terminal end region length L and a value ofsin 35.27, the terminal end region length L can be expressed as aproduct of the distance and 1/sin 35.27, the distance obtained bysubtracting a half of the length of the N conductive type column regionwidth W_(N) from the column depth D. Accordingly, the terminal endregion length L is set to satisfy the numerical formula No. 3.L≧(D−W _(N)/2)/sin 35.27  (Numerical formula No. 3)

Here, L represents the terminal end region length, W_(N) represents theN conductive type column region width, and D represents the columnstructure depth.

Thus, a terminal end region length is defined as the distance from theterminal end 17 of the active region to the PN junction at the columnregion terminal end 16 on the substrate surface. The terminal end 17 isdetermined by the utmost outer periphery of the P⁺ conductive type bodycontact region 8. The N conductive type semiconductor region 21 composedof the active region 13 and the N conductive type silicon single crystalis formed to separate by the terminal end region length L satisfying thenumerical formula No. 3.

In the above structure, the depletion layer spreading from the inside ofthe column region 4 toward the column region terminal end 16 spreads tobe equivalent to the depletion layer spreading from the column region 4toward the substrate depth direction. Accordingly, the electric fieldconcentration at the region facing the narrow side of the columnstructure is prevented so that the breakdown voltage of the verticaltype MOSFET is improved.

(Fourth Embodiment)

FIG. 9A is a cross sectional view showing a vertical type MOSFETaccording to a fourth embodiment of the present invention. Thedifference from the third embodiment is in such a manner that no P⁻conductive type semiconductor region 5 and no N buffer region 12 on thesubstrate surface shown in the cross sectional view in FIGS. 7A and 7Bin the third embodiment exists; instead, the P conductive type bodyregion 6 is disposed in the column region 4.

The layout on the substrate surface, similar to the third embodiment,has a structure corresponding to the VIIA—VIIA cross sectional structurefacing the narrow side of the second semiconductor region 3 having thesecond conductive type shown in FIG. 8. Here, FIG. 9B is described tounderstand this embodiment easily. FIG. 9B shows a structurecorresponding to the VIIB—VIIB cross sectional structure facing the wideside of the second semiconductor region 3 having the second conductivetype shown in FIG. 2A, the structure which is well-known conventionally.

In the fourth embodiment, no P⁻ conductive type semiconductor region 5and no N conductive type buffer region 12 described in the thirdembodiment exist. Therefore, the PN junction surface at the terminal end14 existing on the substrate surface is disposed on the outer periphery,compared with the third embodiment. Specifically, the active region 13and the N conductive type silicon single crystal region 21 are formed tosatisfy the numerical formula No. 4. The numerical formula No. 4 isobtained by adding a term (i.e., D_(B)/tan 35.27) to the numericalformula No. 3. The term has a parameter of the depth (i.e., D_(B)) ofthe P conductive type body region shown in FIG. 9A.L≧{(D−W _(N)/2)/sin 35.27}+(D _(B)/tan 35.27)  (Numerical formula No. 4)

Here, L represents the terminal end region length, W_(N) represents theN conductive type column region width, D represents the column structuredepth, and D_(B) represents the P conductive type body region depth.

Thus, in the fourth embodiment, similar to the third embodiment, thedepletion layer spreading from the inside of the column region 4 towardthe column region terminal end 16 spreads to be equivalent to thedepletion layer spreading in the substrate depth direction. Accordingly,the electric field concentration at the region facing the narrow side ofthe column structure is prevented so that the breakdown voltage of thevertical type MOSFET is improved.

(Fifth Embodiment)

In this embodiment, regarding to a corner of the column region describedin the fourth embodiment, the electric field concentration at the regionfacing the narrow side of the column structure is prevented so that thebreakdown voltage of the vertical type MOSFET is improved. Specifically,as shown in FIG. 10, the narrow side of the column is disposed outsideof a range of the terminal end region length L, the range which is shownas a circular portion separated by the terminal end region length L fromthe active region terminal end 17 viewing from the upper side of thesubstrate.

The relationship of the terminal end region length L described in theabove embodiments can be similarly applied to the corner of the columnregion 4. Specifically, in a case where the terminal end region length Lsatisfies one of the numerical formulas No. 2 to No. 4, the corner ofthe depletion layer circularly spreads toward the outer periphery fromthe starting point of the corner of the active region viewing from theupper side of the substrate when the breakdown voltage is applied to thedevice. At this time, the P conductive type column region terminal end161 is designed to be outside of a range of the terminal end regionlength L, so that the terminal end region length L at the corner of thecolumn region 4 in each embodiment satisfies the numerical formula No.2, No. 3 or No. 4 described in the above embodiments. Accordingly, thestructure described in this embodiment provides that a portion having alow breakdown voltage is prevented from being formed locally in thewhole semiconductor device.

(Other Embodiments)

Regarding to the column region 4, the width (i.e., W_(N) or W_(P)) ofthe P conductive type or the N conductive type column region and theconcentration in the P conductive type or the N conductive type columnregion are not described especially. However, the width (i.e., W_(N) orW_(P)) of the P conductive type or the N conductive type column regionand the concentration in the P conductive type or the N conductive typecolumn region in the whole substrate surface can be constant.

Further, although the present invention is applied to the verticalMOSFET, the present invention can be applied to other verticalsemiconductor devices. Furthermore, although the vertical MOSFET has theN conductive type, the vertical MOSFET can have the P conductive type.

1. Semiconductor equipment having a vertical type semiconductor device,the equipment comprising: a semiconductor substrate having a firstconductive type; a column region including a first semiconductor regionhaving the first conductive type and a second semiconductor regionhaving a second conductive type, wherein the first and the secondsemiconductor regions have predetermined depths in a substrate depthdirection of the semiconductor substrate, respectively, wherein thesecond semiconductor region disposed in the first semiconductor regionhas a polygonal shape including a stripe shape viewing from a substratesurface side, wherein each of the first and the second semiconductorregions includes a plurality of parts separating each other by apredetermined distance, and wherein the first and the secondsemiconductor regions are alternately aligned on the semiconductorsubstrate so that a column structure is provided; a third semiconductorregion disposed on the semiconductor substrate having the firstconductive type and disposed outside of the column region; a fourthsemiconductor region having the second conductive type, wherein thefourth semiconductor region is disposed on the third semiconductorregion, and disposed on the column region or on a range from the columnregion to the outside of the column region; a fifth semiconductor regiondisposed outside of the fourth semiconductor region, and disposed on thethird semiconductor region, wherein the fifth semiconductor regionspreads from a surface of the device to the third semiconductor region;a body region having the second conductive type and disposed on thesubstrate surface side of the third semiconductor region; a sourceregion having the first conductive type; a body contact region havingthe second conductive type; a trench, wherein the source region, thebody contact region and the trench are disposed in the body region; agate insulation layer disposed on a sidewall and a bottom of the trench;and a trench gate provided in such a manner that an electrode isembedded in the trench through the gate insulation layer, wherein thesource region is disposed around the trench gate and disposed on asurface of the body region, the body contact region is disposed on asurface of the body region, the semiconductor substrate and the firstsemiconductor region are electrically connected, the column regionincluding the source region, the body region, the body contact regionand the trench gate provides an active region, the body contact regionhas a terminal end as a terminal end of the active region, the secondsemiconductor region has a terminal end on a narrow side of the secondsemiconductor region in the column region, a distance from the terminalend of the body contact region to the terminal end of the secondsemiconductor region is defined as a terminal end region length of L,the first semiconductor region has a width defined as W₁, and the columnstructure has a depth defined as D, and the terminal end region lengthof L, the first semiconductor region width of W₁ and the columnstructure depth of D satisfy a relationship of L≧D−W₁/2. 2.Semiconductor equipment having a vertical type semiconductor device, theequipment comprising: a semiconductor substrate having a firstconductive type; a column region having a first semiconductor regionhaving the first conductive type and a second semiconductor regionhaving a second conductive type, wherein the first and the secondsemiconductor regions have a predetermined depth in a substrate depthdirection of the semiconductor substrate, wherein the secondsemiconductor region disposed in the first semiconductor region has apolygonal shape including a stripe shape viewing from a substratesurface side, wherein each of the first and the second semiconductorregion includes a plurality of parts separating each other by apredetermined distance, respectively, and wherein the first and thesecond semiconductor regions are alternately aligned on thesemiconductor substrate so that a column structure is provided; a thirdsemiconductor region disposed on the semiconductor substrate having thefirst conductive type and disposed outside of the column region; afourth semiconductor region having the second conductive type, whereinthe fourth semiconductor region is disposed on the third semiconductorregion, and disposed on the column region or on a range from the columnregion to the outside of the column region; a fifth semiconductor regiondisposed outside of the fourth semiconductor region, and disposed on thethird semiconductor region, wherein the fifth semiconductor regionspreads from a surface of the device to the third semiconductor region;a body region having the second conductive type and disposed on thesubstrate surface side of the third semiconductor region; a sourceregion having the first conductive type; a body contact region havingthe second conductive type; a trench, wherein the source region, thebody contact region and the trench are disposed in the body region; agate insulation layer disposed on a sidewall and a bottom of the trench;a trench gate provided in such a manner that an electrode is embedded inthe trench through the gate insulation layer; and a buffer region havingthe first conductive type, and disposed to contact the trench gate, thebody region and the first semiconductor region, wherein the sourceregion is disposed around the trench gate and disposed on a surface ofthe body region, the body contact region is disposed on a surface of thebody region, the trench gate is disposed to reach the buffer region, thesemiconductor substrate and the first semiconductor region areelectrically connected, the column region including the source region,the body region, the body contact region and the trench gate provides anactive region, the body contact region has a terminal end as a terminalend of the active region, the second semiconductor region has a terminalend on a narrow side of the second semiconductor region in the columnregion, a distance from the terminal end of the body contact region tothe terminal end of the second semiconductor region is defined as aterminal end region length of L, the first semiconductor region has awidth defined as W₁, and the column structure has a depth defined as D,and the terminal end region length of L, the first semiconductor regionwidth of W₁ and the column structure depth of D satisfy a relationshipof L≧D−W₁/2.
 3. Semiconductor equipment having a vertical typesemiconductor device, the equipment comprising: a semiconductorsubstrate having a first conductive type; a column region having a firstsemiconductor region having the first conductive type and a secondsemiconductor region having a second conductive type, wherein the firstand the second semiconductor regions have a predetermined depth in asubstrate depth direction of the semiconductor substrate, wherein thesecond semiconductor region disposed in the first semiconductor regionhas a polygonal shape including a stripe shape viewing from a substratesurface side, wherein each of the first and the second semiconductorregions includes a plurality of parts separating each other by apredetermined distance, respectively, and wherein the first and thesecond semiconductor regions are alternately aligned on thesemiconductor substrate so that a column structure is provided; a bodyregion having the second conductive type and disposed on the substratesurface side of the column region; a source region having the firstconductive type; a body contact region having the second conductivetype; a trench, wherein the source region, the body contact region andthe trench are disposed in the body region; a gate insulation layerdisposed on a sidewall and a bottom of the trench; and a trench gateprovided in such a manner that an electrode is embedded in the trenchthrough the gate insulation layer, wherein the source region is disposedaround the trench gate and disposed on a surface of the body region, thebody contact region is disposed on a surface of the body region, thetrench gate is disposed to reach the first semiconductor region, thesemiconductor substrate and the first semiconductor region areelectrically connected, the column region including the source region,the body region, the body contact region and the trench gate provides anactive region, the body contact region has a terminal end as a terminalend of the active region, the second semiconductor region has a terminalend on a narrow side of the second semiconductor region in the columnregion, a distance from the terminal end of the body contact region tothe terminal end of the second semiconductor region is defined as aterminal end region length of L, the first semiconductor region has awidth defined as W₁, and the column structure has a depth defined as D,and the terminal end region length of L, the first semiconductor regionwidth of W₁ and the column structure depth of D satisfy a relationshipof L≧D−W₁/2.
 4. Semiconductor equipment having a vertical typesemiconductor device, the equipment comprising: a semiconductorsubstrate having a (110)-Si surface and a first conductive type; acolumn region having a first semiconductor region having the firstconductive type and a second semiconductor region having a secondconductive type, wherein the first and the second semiconductor regionshave a predetermined depth in a substrate depth direction of thesemiconductor substrate, wherein the second semiconductor regiondisposed in the first semiconductor region has a polygonal shapeincluding a stripe shape viewing from a substrate surface side, whereineach of the first and the second semiconductor regions includes aplurality of parts separating each other by a predetermined distance,respectively, and wherein the first and the second semiconductor regionsare alternately aligned on the semiconductor substrate so that a columnstructure is provided; a third semiconductor region disposed on thesemiconductor substrate having the first conductive type and disposedoutside of the column region; a fourth semiconductor region having thesecond conductive type, wherein the fourth semiconductor region isdisposed on the third semiconductor region, and disposed on the columnregion or on a range from the column region to the outside of the columnregion; a fifth semiconductor region disposed outside of the fourthsemiconductor region, and disposed on the third semiconductor region,wherein the fifth semiconductor region spreads from a surface of thedevice to the third semiconductor region; a body region having thesecond conductive type and disposed on the substrate surface side of thethird semiconductor region; a source region having the first conductivetype; a body contact region having the second conductive type; a trench,wherein the source region, the body contact region and the trench aredisposed in the body region; a gate insulation layer disposed on asidewall and a bottom of the trench; and a trench gate provided in sucha manner that an electrode is embedded in the trench through the gateinsulation layer, wherein the second semiconductor region includes asurface composing an outer shape, the surface including at least onepair of (111)-Si surfaces, the source region is disposed around thetrench gate and disposed on a surface of the body region, the bodycontact region is disposed on a surface of the body region, thesemiconductor substrate and the first semiconductor region areelectrically connected, the column region including the source region,the body region, the body contact region and the trench gate provides anactive region, the body contact region has a terminal end as a terminalend of the active region, the second semiconductor region has a terminalend on a narrow side of the second semiconductor region in the columnregion, a distance from the terminal end of the body contact region tothe terminal end of the second semiconductor region is defined as aterminal end region length of L, the first semiconductor region has awidth defined as W₁, and the column structure has a depth defined as D,and the terminal end region length of L, the first semiconductor regionwidth of W₁ and the column structure depth of D satisfy a relationshipof L≧(D−W₁/2)/sin 35.27.
 5. Semiconductor equipment having a verticaltype semiconductor device, the equipment comprising: a semiconductorsubstrate having a (110)-Si surface and a first conductive type; acolumn region having a first semiconductor region having the firstconductive type and a second semiconductor region having a secondconductive type, wherein the first and the second semiconductor regionshave a predetermined depth in a substrate depth direction of thesemiconductor substrate, wherein the second semiconductor regiondisposed in the first semiconductor region has a polygonal shapeincluding a stripe shape viewing from a substrate surface side, whereineach of the first and the second semiconductor regions includes aplurality of parts separating each other by a predetermined distance,respectively, and wherein the first and the second semiconductor regionsare alternately aligned on the semiconductor substrate so that a columnstructure is provided; a third semiconductor region disposed on thesemiconductor substrate having the first conductive type and disposedoutside of the column region; a fourth semiconductor region having thesecond conductive type, wherein the fourth semiconductor region isdisposed on the third semiconductor region, and disposed on the columnregion or on a range from the column region to the outside of the columnregion; a fifth semiconductor region disposed outside of the fourthsemiconductor region, and disposed on the third semiconductor region,wherein the fifth semiconductor region spreads from a surface of thedevice to the third semiconductor region; a body region having thesecond conductive type and disposed on the substrate surface side of thethird semiconductor region; a source region having the first conductivetype; a body contact region having the second conductive type; a trench,wherein the source region, the body contact region and the trench aredisposed in the body region; a gate insulation layer disposed on asidewall and a bottom of the trench; a trench gate provided in such amanner that an electrode is embedded in the trench through the gateinsulation layer; and a buffer region having the first conductive type,and disposed to contact the trench gate, the body region and the firstsemiconductor region, wherein the second semiconductor region includes asurface composing an outer shape, the surface including at least onepair of (111)-Si surfaces, the source region is disposed around thetrench gate and disposed on a surface of the body region, the bodycontact region is disposed on a surface of the body region, the trenchgate is disposed to reach the buffer region, the semiconductor substrateand the first semiconductor region are electrically connected, thecolumn region including the source region, the body region, the bodycontact region and the trench gate provides an active region, the bodycontact region has a terminal end as a terminal end of the activeregion, the second semiconductor region has a terminal end on a narrowside of the second semiconductor region in the column region, a distancefrom the terminal end of the body contact region to the terminal end ofthe second semiconductor region is defined as a terminal end regionlength of L, the first semiconductor region has a width defined as W₁,and the column structure has a depth defined as D, and the terminal endregion length of L, the first semiconductor region width of W₁ and thecolumn structure depth of D satisfy a relationship of L≧(D−W₁/2)/sin35.27.
 6. Semiconductor equipment having a vertical type semiconductordevice, the equipment comprising: a semiconductor substrate having a(110)-Si surface and a first conductive type; a column region having afirst semiconductor region having the first conductive type and a secondsemiconductor region having a second conductive type, wherein the firstand the second semiconductor regions have a predetermined depth in asubstrate depth direction of the semiconductor substrate, wherein thesecond semiconductor region disposed in the first semiconductor regionhas a polygonal shape including a stripe shape viewing from a substratesurface side, wherein each of the first and the second semiconductorregions includes a plurality of parts separating each other by apredetermined distance, respectively, and wherein the first and thesecond semiconductor regions are alternately aligned on thesemiconductor substrate so that a column structure is provided; a bodyregion having the second conductive type and disposed on the substratesurface side of the column region; a source region having the firstconductive type; a body contact region having the second conductivetype; a trench, wherein the source region, the body contact region andthe trench are disposed in the body region; a gate insulation layerdisposed on a sidewall and a bottom of the trench; and a trench gateprovided in such a manner that an electrode is embedded in the trenchthrough the gate insulation layer, wherein the second semiconductorregion includes a surface composing an outer shape, the surfaceincluding at least one pair of (111)-Si surfaces, the source region isdisposed around the trench gate and disposed on a surface of the bodyregion, the body contact region is disposed on a surface of the bodyregion, the trench gate is disposed to reach the buffer region, thesemiconductor substrate and the first semiconductor region areelectrically connected, the column region including the source region,the body region, the body contact region and the trench gate provides anactive region, the body contact region has a terminal end as a terminalend of the active region, the second semiconductor region has a terminalend on a narrow side of the second semiconductor region in the columnregion, a distance from the terminal end of the body contact region tothe terminal end of the second semiconductor region is defined as aterminal end region length of L, the first semiconductor region has awidth defined as W₁, the column structure has a depth defined as D, andthe body region has a depth defined as D_(B), and the terminal endregion length of L, the first semiconductor region width of W₁, thecolumn structure depth of D and the body region depth of D_(B) satisfy arelationship of L≧{(D−W₁/2)/sin 35.27}+(D_(B)/tan 35.27).